35 lines
749 B
Systemverilog
35 lines
749 B
Systemverilog
module timebase
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(input logic clk,
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input logic reset,
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output logic [4:0] count);
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logic [16:0] internal_count,next_internal_count;
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logic [4:0] next_count;
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always_ff @(posedge clk) begin
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if(reset)begin
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count <=0;
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internal_count <=0 ;
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end
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else begin
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count <= next_count;
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internal_count <= next_internal_count;
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end
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end
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always_comb
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begin
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if(internal_count ==? 100000) begin
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next_internal_count=0;
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if(count ==? 19)
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next_count = 0;
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else
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next_count = count+1;
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end
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else begin
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next_internal_count = internal_count+1;
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next_count=count;
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end
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end
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endmodule
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