82 lines
2.0 KiB
Systemverilog
82 lines
2.0 KiB
Systemverilog
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module motorcontrol
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(input logic clk,
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input logic reset,
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input logic direction,
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input logic [20:0] count_in,
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output logic pwm);
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// typedef enum logic [1:0] { motor_off, motor_cw, motor_ccw } motor_controller_state;
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// motor_controller_state state,next_state;
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//
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// always_ff @(posedge clk)
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// if (reset)
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// state <= motor_off;
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// else
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// state <= next_state;
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//
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// always_comb //state logic
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// begin
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// if(direction ==? 0)
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// next_state = motor_ccw;
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// else
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// next_state = motor_cw;
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// end
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//
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// always_comb //PWM logic
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// begin
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// case(state)
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// motor_off:
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// pwm=0;
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// motor_ccw:
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// begin
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// if(count_in <= 100000)
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// pwm=1;
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// else
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// pwm=0;
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// end
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// motor_cw:
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// begin
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// if(count_in <= 200000 )
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// pwm=1;
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// else
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// pwm=0;
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// end
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// endcase
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//
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// end
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typedef enum logic { pwm_off, pwm_on } motor_controller_state;
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motor_controller_state state,next_state;
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always_ff @(posedge clk) begin
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if(reset)
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state<=pwm_off;
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else
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state<= next_state;
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end
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always_comb begin
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case(state)
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pwm_off:
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begin
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pwm=0;
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if(count_in ==? 0) begin
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next_state=pwm_on;
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end
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end
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pwm_on:
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begin
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pwm=1;
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if((direction ==? 0) && (count_in >= 100000)) begin //CCW
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next_state=pwm_off;
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end
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else if((direction ==? 1) && (count_in >= 200000)) begin
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next_state=pwm_off;
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end
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else
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next_state=pwm_on;
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end
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endcase
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end
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endmodule
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