24 lines
417 B
Systemverilog
24 lines
417 B
Systemverilog
module timebase
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(input logic clk,
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input logic reset,
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output logic [20:0] count);
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logic [20:0] next_count;
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always_ff @(posedge clk)
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begin
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if(reset)
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count <= 0;
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else
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count <= next_count;
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end
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//always_comb begin
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// if(count==?2000000)
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// next_count=0;
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// else
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assign next_count=count+1;
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//end
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endmodule
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