32 lines
797 B
Systemverilog
32 lines
797 B
Systemverilog
module inputbuffer
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(input logic clk,
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input logic sensor_l_in,
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input logic sensor_m_in,
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input logic sensor_r_in,
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output logic sensor_l_out,
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output logic sensor_m_out,
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output logic sensor_r_out);
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logic [2:0] sensor_reg;
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logic buffer_l,buffer_m,buffer_r;
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always_ff @(posedge clk)begin
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sensor_reg <= {sensor_l_in,sensor_m_in,sensor_r_in};
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end
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always_ff @(posedge clk)begin
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{sensor_l_out,sensor_m_out,sensor_r_out} <= sensor_reg;
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end
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//always_ff @(posedge clk)begin
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// buffer_l <= sensor_reg[0];
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// buffer_m <= sensor_reg[1];
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// buffer_r <= sensor_reg[2];
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//end
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//assign sensor_l_out = buffer_l;
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//assign sensor_m_out = buffer_m;
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//assign sensor_r_out = buffer_r;
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endmodule
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