18 lines
284 B
Systemverilog
18 lines
284 B
Systemverilog
`timescale 1 ns/ 1 ps
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module blinking_led_tb ();
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logic clk = 1'b1, rst = 1'b1, short = 1'b0, led;
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always begin
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#5 clk = ~clk;
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end
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initial begin
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#20 rst = 1'b0;
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#1000000000 short = 1'b1;
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end
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blinking_led dut(.*);
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endmodule |