30 lines
732 B
Systemverilog
30 lines
732 B
Systemverilog
module blinking_led (
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input logic clk,
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input logic rst,
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input logic short,
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output logic led
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);
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logic [26:0] count;
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logic led_long, led_short;
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// up-counter
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// resets itself every 100 million clock cycles (1 sec with a 100 MHz clock)
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always_ff @(posedge clk) begin
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if (rst)
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count <= 0;
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else
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if (count >= 100_000_000 - 1)
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count <= 0;
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else
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count <= count + 1;
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end
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// derive 0.5 sec and 0.25 sec pulses from counter
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assign led_long = (count < 50_000_000);
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assign led_short = (count < 25_000_000);
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// choose which pulse to display on LED based on signal "short"
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assign led = short ? led_short : led_long;
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endmodule |