107 lines
2.8 KiB
Systemverilog
107 lines
2.8 KiB
Systemverilog
module controller
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(input logic clk,
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input logic reset,
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input logic sensor_l,
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input logic sensor_m,
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input logic sensor_r,
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input logic [20:0] count_in,
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output logic count_reset,
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output logic motor_l_reset,
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output logic motor_l_direction,
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output logic motor_r_reset,
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output logic motor_r_direction);
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// actual FSM control
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typedef enum logic [2:0] { off, sharp_left, gentle_left, forward, gentle_right, sharp_right } controller_state;
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controller_state state,next_state;
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always_ff @(posedge clk) begin
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if(reset)begin
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state <= off;
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count_reset<=1;
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end
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else begin
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state <= next_state;
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count_reset<=0;
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end
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end
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//state logic
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always_comb begin
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case ({sensor_l,sensor_m,sensor_r})
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3'b000:
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next_state = forward;
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3'b001:
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next_state = gentle_left;
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3'b010:
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next_state = forward;
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3'b011:
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next_state = sharp_left;
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3'b100:
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next_state = gentle_right;
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3'b101:
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next_state = forward;
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3'b110:
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next_state = sharp_right;
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3'b111:
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next_state = forward;
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endcase
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end
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//output logic
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always_comb begin
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case(state)
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off:
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begin
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motor_l_reset=1;
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motor_r_reset=1;
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end
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forward:
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begin
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motor_l_direction=1;
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motor_r_direction=0;
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motor_l_reset=0;
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motor_r_reset=0;
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end
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gentle_left:
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begin
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motor_l_direction=0;
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motor_r_direction=0;
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motor_l_reset=1;
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motor_r_reset=0;
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end
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sharp_left:
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begin
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motor_l_direction=0;
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motor_r_direction=0;
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motor_l_reset=0;
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motor_r_reset=0;
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end
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gentle_right:
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begin
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motor_l_direction=1;
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motor_r_direction=0;
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motor_l_reset=0;
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motor_r_reset=1;
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end
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sharp_right:
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begin
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motor_l_direction=1;
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motor_r_direction=1;
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motor_l_reset=0;
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motor_r_reset=0;
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end
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default:
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begin
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motor_l_reset=1;
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motor_r_reset=1;
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end
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endcase
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end
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endmodule
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